general description the max3971 is a compact, low-power, 10.3gbps limit- ing amplifier. it accepts signals over a wide range of input voltage levels and provides constant-level output volt- ages with controlled edge speeds. it functions as a data quantizer. the output of the amplifier is a 250mv p-p differ- ential cml signal with a 100 ? differential termination. the max3971 is designed to work with the max3970, a 10.3gbps transimpedance amplifier (tia). the limiting amplifier operates on a single +3.3v supply and con- sumes only 155mw. the part functions over the 0? to +85? temperature range. it also has a disable function that allows the outputs to be squelched if required by the application. the max3971 is offered in die form and in a compact 4mm x 4mm, 20-pin qfn plastic package. applications 10-gigabit ethernet optical receivers vsr oc-192 receivers 10-gigabit fibre channel receivers ____________________________features ? single +3.3v power supply ? 155mw power consumption ? 9.5mv p-p input sensitivity ? 800mv p-p input overload ? 3.4ps p-p deterministic jitter ? dice and 4mm x 4mm qfn packages ? output disable feature max3971 +3.3v, 10.3gbps limiting amplifier ________________________________________________________________ maxim integrated products 1 max3971 max3970 tia 100 ? in+ gndin- gndin+ in- supply filter v cc 1v cc 2v cc 3 out+ out- cz- cz+ 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f disable 100 ? +3.3v +3.3v t ypical application circuit * dice are designed to operate over a 0? to +110? junction temperature (t j ) range, but are tested and guaranteed at t a = +25?. ordering information part temp. range pin-package pkg code MAX3971UGP 0? to +85? 20 qfn g2044-4 max3971u/d 0? to +85? dice* 19-2086; rev 2; 5/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet.
max3971 +3.3v, 10.3gbps limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings supply voltage, v cc1 , v cc2 , v cc3 .......................-0.5v to +0.5v voltage at in+, in-, disable, cz+, cz-, out+, out-........................+0.5v to (v cc + 0.5v) differential voltage between cz+ and cz- ...........................?v differential voltage between in+ and in-...........................?.5v continuous power dissipation (t a = +85?) 20-lead qfn (derate 20mw/? above +85?) ..............1.3w operating ambient temperature range .............-40? to +85? storage temperature range .............................-55? to +150? die attach temperature...................................................+400? lead temperature (soldering, 10s) .................................+300? stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v cc = +3.0v to +3.6v, t a = 0? to +85?. typical values are at v cc = +3.3v, output load = 50 ? to v cc , t a = +25?, unless other- wise noted. data mark density is 50%.) parameter symbol conditions min typ max units supply current i cc 47 85 ma small-signal bandwidth bw 10 ghz low-frequency cutoff cz = 0.1? 40 160 khz data rate 10 gbps 10mv p-p input, k28.5 pattern at 10.3gbps (note 1) 8 20mv p-p input, k28.5 pattern at 10.3gbps (note 1) 4.7 14 deterministic jitter 800mv p-p input, k28.5 pattern at 10.3gbps (note 1) 3.4 7 ps p-p random jitter 20mv p-p to 800mv p-p (note 2) 0.7 1.0 ps rms transition time, output t r , t f 20% to 80%, out+, out- 20 30 ps input sensitivity v in-min ber = 1e-12, 2 23 - 1prbs, 10.3gbps 9.5 mv p-p input overload v in-max 800 mv p-p data input resistance r in single-ended 42 52 58 ? v od1 disable high 1 50 differential data output-voltage swing v od2 disable low 190 250 400 mv p-p data output common-mode voltage v cm v cc - 0.75 v output resistance r out single-ended 42 52 58 ? data output offset when disable is high 75 mv p-p disable input current high = v cc , low = gnd 0.05 1 ma disable input high voltage 2.8 v disable input low voltage 1.4 v note 1: deterministic jitter is measured with a k28.5 pattern (0011 1110 1011 0000 0101). it is the peak-to-peak deviation from the ideal time crossings, measured at the zero-level crossings of the differential output. note 2: random jitter is measured with the minimum input signal applied. to achieve a bit error rate of 10 -12 , the peak-to-peak ran- dom jitter is 14.1 times the rms random jitter.
max3971 +3.3v, 10.3gbps limiting amplifier _______________________________________________________________________________________ 3 40 45 50 55 60 65 70 020 10 30 40 50 60 70 80 90 supply current vs. temperature max3971 toc01 temperature ( c) supply current (ma) 20ps/div output eye diagram (input signal = 800mv p-p at 10.3gbps) 50mv/div max3971 toc02 20ps/div output eye diagram (input signal = 9mv p-p at 10.3gbps) 50mv/div max3971 toc03 03040 10 20 50 60 70 80 90 transition time vs. temperature (20% to 80%) max3971 toc04 temperature ( c) time (ps) 19 20 21 22 (1) (2) (1) v cc = +3.0v, input = 800mv p-p (2) v cc = +3.6v, input = 800mv p-p 7 8 9 10 11 10 30 50 70 20 40 60 80 90 input sensitivity vs. temperature (for bit-error ratio of 1e-12) max3971 toc07 temperature ( c) signal input level (mv p-p ) 60 50 40 30 20 10 70 0 80 90 deterministic jitter vs. temperature (800mv p-p input k28.5 pattern at 10.3gbps) max3971 toc05 temperature ( c) jitter (ps p-p ) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 4.8 4.6 4.4 4.2 5.0 4.0 (1) (2) (1) v cc = +3.0v (2) v cc = +3.6v 60 50 40 30 20 10 70 0 80 90 deterministic jitter vs. temperature (10mv p-p input k28.5 pattern at 10.3gbps) max3971 toc06 temperature ( c) jitter (ps p-p ) 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 5.0 7.8 7.6 7.4 7.2 8.0 7.0 (1) (2) (1) v cc = +3.0v (2) v cc = +3.6v -50 -20 -30 -40 -10 0 10 100 4100 2100 6100 8100 10,100 input return (s11) input signal = -20dbm max3971 toc08 frequency (mhz) gain (db) -50 -20 -30 -40 -10 0 10 100 4100 2100 6100 8100 10,100 output return (s22) input signal = -20dbm max3971 toc09 frequency (mhz) gain (db) t ypical operating characteristics (v cc = +3.3v, output load = 50 ? to v cc , t a = +25?, unless otherwise noted.)
max3971 +3.3v, 10.3gbps limiting amplifier 4 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v cc = +3.3v, output load = 50 ? to v cc , t a = +25?, unless otherwise noted.) 0 20 10 40 30 50 60 11 0 100 1000 power-supply rejection ratio vs. frequency max3971 toc10 frequency (mhz) psrr (db) 0 20 10 40 30 50 60 1 100 10 1000 10,000 common-mode rejection ratio vs. frequency max3971 toc11 frequency (mhz) cmmr (db) pin name function 1 gndin+ input ground for shielding input signal in+. not connected internally. 2 in+ noninverting input signal 3 in- inverting input signal 4 gndin- input ground for shielding input signal in-. not connected internally. 5, 7, 9, 10 n.c. no connection. leave unconnected. 6, 8, 11 gnd ground 12, 15 v cc 3 output circuitry power supply 13 out- inverting output of amplifier 14 out+ noninverting output of amplifier 16 disable when high, the outputs are disabled 17 v cc 2 power supply to circuitry other than input and output circuits 18 cz+ filter capacitor for offset correction. attach other side of a capacitor to pin 19. see the detailed description . 19 cz- see pin 18. 20 v cc1 input circuitry power supply ep exposed pad exposed pad. must be soldered to supply ground for proper electrical and thermal operation. pin description
detailed description and applications information figure 1 is a functional diagram of the max3971 limit- ing amplifier.the signal path consists of an input buffer followed by a gain stage and output amplifier. a feed- back loop provides offset correction by driving the average value of the differential output to zero. gain stage and offset correction the limiting amplifier provides approximately 50db gain. this large gain makes the amplifier susceptible to small dc offsets, which cause deterministic jitter. a low-frequency loop is integrated into the limiting amplifier to reduce output offset, typically to less than 2mv. the external capacitor cz is required to set the low-fre- quency cutoff for the offset correction loop and for sta- bility. the time constant of the loop is set by the product of an equivalent 20k ? on-chip resistor and the value of the off-chip capacitor, cz. for stable opera- tion, the minimum value of cz is 0.01?. to minimize pattern-dependent jitter, cz should be as large as pos- sible. for 10-gigabit ethernet applications, the typical value of cz is 0.1?. keep cz as close to the package as possible. cml input circuit the input buffer is designed to accept cml input sig- nals such as the output from the max3970 transimped- ance amplifier. an equivalent circuit for the input is shown in figure 2. dc-coupling the inputs is not recom- mended because doing so prevents the part? offset correction circuitry from working properly. thus, ac- coupling capacitors are required on the input. cml output circuit an equivalent circuit for the output network is shown in figure 3. it consists of two 50 ? resistors connected to v cc driven by the collectors of an output differential transistor pair (q1 and q2). the differential output sig- nals are clamped by transistors q3 and q4 when the disable input is high. disable function a logic signal can be applied to the disable pin to squelch the output signal. when the output is disabled, an offset is added to the output, preventing the follow- ing stage from oscillating (if dc-coupled). max3971 +3.3v, 10.3gbps limiting amplifier _______________________________________________________________________________________ 5 max3971 cz- cz+ lowpass filter cz offset correction amp input amplifier gain 50db output amplifier out+ out- in+ gndin+ gndin- in- disable figure 1. functional diagram v cc 1 50 ? 50 ? in+ gndin+ gndin- in- esd structures figure 2. cml input equivalent circuit v cc 3 50 ? 50 ? q1 q2 q3 q4 out+ out- disable data esd structures figure 3. cml input equivalent circuit showing clamping circuit for squelching the output signal
max3971 layout considerations circuit board layout and design can significantly affect the max3971? performance. use good high-frequency techniques, including fixed-impedance transmission lines for the high-frequency data signal. use a multilay- er board with solid ground plane. minimize the induc- tance between max3971 and the ground plane. the max3971 uses three power supply pins (v cc 1, v cc 2, v cc 3). the input circuitry of the max3971 is supplied by v cc 1. the output drivers have a separate supply (v cc 3), which usually has large pulsing cur- rents. all other circuitry is powered by v cc 2. it is possi- ble to simply connect the three pins together. however, better isolation of the input circuitry is ensured by using a supply filter. for optimal isolation, figure 4 shows a possible supply filtering circuit. element l, a ferrite bead, provides isolation between a noisy v cc 3 and sensitive v cc 1. +3.3v, 10.3gbps limiting amplifier 6 _______________________________________________________________________________________ +3.3v max3971 v cc 1v cc 2v cc 3 c = 0.001 fc = 0.001 fc = 0.001 f l supply filter figure 4. power-supply filter chip information transistor count: 1803 proccess: sige bipolar substrate: electrically isolated 19 cz- 20 v cc 1 18 cz+ 17 v cc 2 16 disable 9 n.c. 10 n.c. 8 gnd 7 n.c. 6 gnd 4 gndin- 5 n.c. 3 in- 2 in+ 1 gndin+ 14 out+ 15 v cc 3 13 out- 12 v cc 3 11 gnd max3971 20 qfn pin configuration
max3971 +3.3v, 10.3gbps limiting amplifier _______________________________________________________________________________________ 7 gndin+ in+ in- gndin- n.c. v cc 3 out+ out- v cc 3 gnd gnd n.c. gnd n.c. n.c. v cc 1 cz- cz+ v cc 2 disable 0.049" (1.25mm) 0.045" (1.15mm) chip topography
max3971 +3.3v, 10.3gbps limiting amplifier 8 _______________________________________________________________________________________ max3971 pin number x dimension (microns) y dimension (microns) 10 672 20 546 30 420 40 294 50 168 6 163.8 0 7 289.8 0 8 415.8 0 9 541.8 0 10 667.8 0 11 884.8 168 12 884.8 294 13 884.8 420 14 884.8 546 15 884.8 672 16 667.8 772.8 17 541.8 772.8 18 415.8 772.8 19 289.8 772.8 20 163.8 772.8 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 5 4 3 2 1 max3971 (0,0) x y all dimensions are in microns. pad dimensions: passivation opening: 94.4 microns 94.4 microns metal: 102.4 microns 102.4 microns all measurements specify the lower left corner of the pad chip topography (continued)
12,16,20, 24l qfn.eps e 1 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm max3971 +3.3v, 10.3gbps limiting amplifier _______________________________________________________________________________________ 9 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max3971 +3.3v, 10.3gbps limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. e 2 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
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